In conventional systems, Input/Output (I/O) devices use interrupts to notify a host stack of various events, such as transmit/receive completions. An interrupt may be described as a signal from a device attached to a computer or from a program executing on the computer that causes the operating system of the computer to stop current processing and handle the interrupt. An I/O device may be described as a device that is part of a host system and that is attached to an I/O fabric. The host system uses I/O devices in performing I/O operations (e.g., network I/O operations, storage I/O operations, etc.). A host stack may be described as software that includes applications, libraries, drivers, and an operating system that run on host processors (Central Processing Units or “CPUs”) of a host system.
In some systems, upon an interrupt from an I/O device, an I/O device driver executing at the host system runs an Interrupt Service Routine (ISR) that checks the state of an I/O device interrupt for each I/O device, one at a time. Then, if a particular I/O device generated the interrupt, the ISR disables interrupts so that the same I/O device cannot generate another interrupt, acknowledges the interrupt, processes the interrupt, and enables interrupts so that the I/O device can generate another interrupt. Typically, an I/O device has registers for interrupt status/cause, masking, and acknowledgement. Thus, the ISR performs an I/O read of the register across a bus for interrupt status/cause to determine whether a particular I/O device generated the interrupt and to determine the type of interrupt. The ISR performs I/O writes across the bus to the register for masking to disable and enable the interrupts. Additionally, the ISR performs an I/O write across the bus to the register for acknowledgement to acknowledge the interrupt. I/O reads and I/O writes go across the bus connecting the I/O device to the host system. Such I/O reads and I/O writes across the bus for interrupt processing may degrade system performance and result in interrupt processing latency and system overhead. Also, the I/O reads and I/O writes may be Memory Mapped I/O (MMIO) reads/writes.
In conventional systems, interrupt processing related overhead to processor is not scalable with processor speed due, for example, to memory mapped IO (MMIO) reads/writes and context switches. Additionally, efficient load balancing of interrupts across multiple processors in a multiprocessor system, especially for packet receive processing in standard operating systems, has become a focus point lately. The impact of interrupts for high performance devices, such as 10 G Transmission Control Protocol (TCP) Offload Engine (TOE)/Remote Direct Memory Access (RDMA) Network Interface Controller (RNIC), also causes problems.
Notwithstanding conventional techniques for interrupt processing, there is a need in the art for improved interrupt processing.